The continual demand to enhanced integrated circuit (IC) performance has resulted in a reduction of semiconductor device geometries, and continual efforts to operate semiconductor devices over a wide range of voltages. A large variety of power semiconductor products in the 20-200V range are fabricated using N or P channel drain-extended field effect and more particularly metal-oxide-semiconductor (DEMOS) transistor devices, or lateral double diffused MOS (LDMOS) devices. These devices are advantageous for System-On-Chip circuit integration using mixed voltages and devices types including, for example, low-voltage MOS devices for digital circuits, memories, bipolar and HVMOS/DEMOS components for analog mixed signal circuits, and LDMOS for power drivers. Frequent fields of application include automotive, consumer, mobile, medical and communication electronics.
Lateral DEMOS and LDMOS present the advantage of having a breakdown voltage which is scalable by drain extension layout, as opposed to vertical or quasi-vertical devices which are optimized for a single drain thickness. DEMOS and LDMOS designs generally require the simultaneous optimization of several electrical parameters. These parameters can include the breakdown voltage (BDV), specific on-resistance (Rsp=on-state resistance in linear regime times device area), switching speed (e.g., as represented by the Rsp*Qgd quality factor, where Qgd is the gate-drain charge), and Safe Operating Area (SOA). Compromises in the value of one or more of these parameters, or to the dimensions of the device, generally need to made in order for the device to work in the SOA that it was intended for.
FIG. 1A is a cross-sectional view of a conventional LDMOS transistor 100, while FIG. 1B is a top view of LDMOS transistor 100 showing alternating n+ source/p+ contacts to the body region along the width of LDMOS transistor 100. An n-type buried layer NBL 11 is formed over p-type substrate 10 having a p-type EPI layer 13 thereon. A counter-doping n-type deep n-well DNWELL region 14 is formed in the p-type epitaxial layer 13, and extends over NBL 11. An n-type well region of higher doping as compared to DNWELL 14 referred to as SNWELL 15 is formed in DNWELL 14 and extends over n-type buried layer 11. The SNWELL 15 is an optional layer in an LDMOS, but can be used as a drain doping buffer improving the device SOA under high gate and drain voltage conditions. A p-type body region 16 is formed in p-epi 13. The DNWELL region 14 overlaps at least a portion of the p-type body region 16. An n+-type source region 18 and a p+ contact region 19 are formed in p-type body region 16. An n+-type drain region 20 which may be of same doping profile as n+-type source region 18 is formed in SNWELL. Although not shown, additional layers of p or n type can be added to the drain extension of LDMOS transistor 100, for example a p-type RESURF (reduced surface field) region connected to body region 16 or floating under portion of the DNWELL 14, or an additional n-type doping buffer towards the drain 20.
A thin gate dielectric layer 21 extends over both a surface portion of p-type body region 16 and the surface of DNWELL region 14. An electrically conductive gate electrode layer 22 extends over gate dielectric layer 21 and the upper portion of a thick field oxide (e.g. a Shallow Trench Isolation (STI) oxide) layer 23 on the side of its source 18. The surface of the p-body region 16 thus provides the channel region for LDMOS transistor 100, which means the channel region is entirely in the horizontal (lateral) direction. A source electrode 24 is in contact with p+-type contact region 19 and n+-type source contact region 18, and a drain electrode 25 is in contact with n+-type drain contact region 20. Gate electrode layer 22, source electrode 24, and drain electrode 25 are generally electrically isolated from one another by an interlayer dielectric (ILD) film (not shown).
The STI oxide 23 (or locally oxidized silicon (LOCOS) in other technologies) is generally necessary to protect the thin gate dielectric edge on the drain side as it would otherwise suffer dielectric breakdown, or progressive degradation during operation. The gate extent (defined herein as the spacing between the output of the channel (the drain end of the p-body 16) and the source side edge of the STI oxide 23) must be large enough to make sure that the LDMOS body-to-drain junction does not block the output of the channel by abutting against the edge of STI 23. The gate extent contributes to the source drain pitch and thus to Rsp. Moreover, this overlap of the gate electrode over the thin gate oxide has a high parasitic gate to drain capacitance which slows down device switching. Finally, the channel itself contributes some pitch length and thus affects RSP somewhat. What is needed is a transistor design wherein the RSP and Qgd are reduced while still providing the required breakdown voltage and SOA.